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HD74LS191
Synchronous Up / Down 4-bit Binary Counter (single clock line)
REJ03D0453-0200 Rev.2.00 Feb.18.2005 Synchronous operation is provided by having all flip-flops clocked simultaneously so that the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input is high. The direction of the count is determined by the level of the down / up input. When low, the counter counts up and when high, it counts down. Level changes at the down / up input should be made only when the clock input is high. This counter is fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. The clock, down / up, and load inputs are buffered to lower the drive requirement which significantly reduces the number of clock drivers, etc., required for long parallel words. Two outputs have been made available to perform the cascading function; ripple clock and made available to perform the cascading function; ripple clock and maximum / minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycles to the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum / minimum count output can be used to accomplish look-ahead for high-speed operation.
Features
* Ordering Information
Part Name HD74LS191P HD74LS191FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.2.00, Feb.18.2005, page 1 of 10
HD74LS191
Pin Arrangement
Data B Input QB Outputs QA Enable G Inputs Down/Up QC Outputs QD GND 7 8
QD D C
1
B
16
QB QA G Dn/Up QC A CK Ripple Clock Max/ Min Load
VCC Data A Inputs Clock Ripple Clock Max/Min Load Data C Data D Inputs Outputs
2 3 4 5 6
15 14 13 12 11 10 9
(Top view)
Rev.2.00, Feb.18.2005, page 2 of 10
HD74LS191
Block Diagram
Clock Down/Up Data Input A Preset J QA Enable G CK K QA Clear Ripple Clock Max/Min Output
Output QA
Data Input B
Preset J QB CK K QB Clear
Output QB
Data Input C Preset J QC CK K QC Clear Output QC
Data Input D Preset J QD CK K QD Clear Load Output QD
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Rev.2.00, Feb.18.2005, page 3 of 10
HD74LS191
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Load pulse width Setup time Hold time Enable time Symbol VCC IOH IOL Topr clock tw (CK) tw (Load) tsu th (data) tenable Min 4.75 -- -- -20 0 25 35 20 3 40 Typ 5.00 -- -- 25 -- -- -- -- -- -- Max 5.25 -400 8 75 20 -- -- -- -- -- Unit V A mA C MHz ns ns ns ns ns
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH min. 2.0 -- 2.7 -- -- -- -- -- -- -- -- typ.* -- -- -- -- -- -- -- -- -- -- -- max. -- 0.8 -- 0.4 0.5 60 20 -1.2 -0.4 0.3 0.1 Unit V V V V A mA mA Condition
Output voltage VOL Enable Others Enable Others Enable Others IIH IIL II
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
Input current
Short-circuit output IOS -20 -- -100 mA current Supply current** ICC -- 20 35 mA Input clamp voltage VIK -- -- -1.5 V Notes: * VCC = 5 V, Ta = 25C ** ICC is measured with all outputs open and all inputs grounded.
Rev.2.00, Feb.18.2005, page 4 of 10
HD74LS191
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Symbol max tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Inputs Clock Load Data A, B, C, D Clock Clock Clock Down / Up Down / Up Enable Outputs QA, QB, QC, QD QA, QB, QC, QD QA, QB, QC, QD Ripple Clock QA, QB, QC, QD Max / Min Ripple Clock Max / Min Ripple Clock min. 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- typ. 25 22 33 20 27 13 16 16 24 28 37 30 30 21 22 21 22 max. -- 33 50 32 40 20 24 24 36 42 52 45 45 33 33 33 33 Unit MHz ns ns ns ns ns ns ns ns CL = 15 pF, RL = 2 k Condition
Propagation delay time
Rev.2.00, Feb.18.2005, page 5 of 10
HD74LS191
Count Sequences
Load A B C D Clock Down/Up Enable G QA QB QC QD Max/Min Ripple Clock
13 Load
14
15
0
1
2 Inhibit
2
1
0
15
14
13
Count Up
Count Down
Illustrated below is the following sequence: 1. Load (preset) to binary thirteen. 2. Count up to fourteen, fifteen (maximum), zero, one and two. 3. Inhibit 4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen.
Rev.2.00, Feb.18.2005, page 6 of 10
HD74LS191
Testing Method
Test Circuit
VCC
Output 4.5V Ripple Clock Enable Down/Up Clock A B C D Load QB Output QC Output QD Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. QA Output Same as Load Circuit 1. Output Max/Min Output Same as Load Circuit 1. RL Load circuit 1
CL
Input P.G. Zout = 50
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Waveforms 1
tTLH Data Input 10% tsu Load Input 90% 90% 1.3V 90% 1.3V 10% tsu 3V 1.3V 10% tTLH Output VOL 1.3V 10% tTLH VOH 90% 0V 0V tTHL 3V
Note:
Input pulse: tTLH, tTHL 10 ns, PRR = 1 MHz, duty cycle 50%
Rev.2.00, Feb.18.2005, page 7 of 10
See Testing Table
HD74LS191 Waveforms 2 LoadQ, DataQ
3V Load 1.3V 1.3V 0V 3V Data (A to D) 1.3V 1.3V 0V VOH Output Q 1.3V tPLH tPHL 1.3V tPLH 1.3V tPHL 1.3V VOL
Note:
Conditions on other inputs are irrelevant.
Waveforms 3 GRipple CK, CKRipple CK, Down / UpRipple CK, Down / UpMax / Min
3V Load 0V 3V Down/Up 1.3V 1.3V 0V 3V Clock 1.3V 1.3V 0V 3V G 0V tPHL tPLH tPHL tPLH VOH Ripple/Clock 1.3V 1.3V tPLH 1.3V 1.3V VOL tPHL VOH Max/Min 1.3V 1.3V VOL
Rev.2.00, Feb.18.2005, page 8 of 10
HD74LS191 Waveforms 4 ClockQ
3V Load 0V 3V Data (A to D) 0V 3V Down/Up 0V 3V Clock 1.3V 1.3V 0V Q Enable = 0V VOH 1.3V tPLH 1.3V VOL tPHL
Waveforms 5 ClockMax / Min
3V Load 0V 3V A Inputs B, C, D 0V 3V Down/Up 0V 3V Clock 1.3V 1.3V 1.3V 1.3V 0V Max/Min Enable = 0V tPLH VOH 1.3V 1.3V tPHL tPLH 1.3V 1.3V VOL tPHL 0V 3V
Rev.2.00, Feb.18.2005, page 9 of 10
HD74LS191
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Feb.18.2005, page 10 of 10
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